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NT68P61A 8-bit microcontroller for monitor (24k otp rom type) 1v1.0 features ? 40 pin dip & 42 pin sdip package ? operating voltage range: 4.5v to 5.5v ? cmos technology for low power consumption ? crystal oscillator or ceramic res onator* available ? 6502 8-bit cmos cpu core ? 8mhz operation of frequency ? 24k bytes of otp (one time programming) rom ? 256 bytes of ram (which stores edid for ddc1/2b) ? one 8-bit pre-loadable base timer ? 14 channels of 8 bit pwm outputs: 6 channel with 5v open drain and 8 channel with 12v open drain ? 2 channel a/d converters with 6-bit resolution ? 24 bi-directional i/o port pins and 1 i/p pin ? hsync/vsync signal processor ? hardware sync signals polarity & freq. evaluator ? built-in i 2 c bus interface ? supporting vesa ddc1/2b function ? six-interrupt sources - intv (vsync int) - inte (external int with rising edge trigger) - intmr (timer int ) - inta (slave address matched int) - intd (shift register int) - ints (scl go-low int) ? hardware watch-dog timer function ? built-in low voltage reset circuit (lvrc) general description NT68P61A is a monitor component m c for auto-sync and digital controlled applications. it contains a 6502 8-bit cpu core, 256 bytes of ram used as working ram and stack area, 24k bytes of otp rom**, 14-channel 8- bit pwm d/a converters, 2-channel a/d converters for key detection saving i/o pins, one 8 bit pre-l oadable base timer, internal hsync and vsync signals processor providing mode detection, watch-dog timer preventing system from abnormal operation, and an i 2 c bus interface. the lvrc enables NT68P61A operate properly. users can store edid data in the 128 bytes of ram for ddc1/2b, so that users can save the cost of dedicated eeprom for edid. half frequency output function can save external one-shot circuit. all of these designs create savings in component costs. * the frequency deviation of ceramic resonator has +/- 6% maximum. ** the nt6861 (mask rom type) w ill provide 4/8/12/16/24k bytes program rom.
NT68P61A 2 pin configuration [oe] dac2 dac1 dac0 [db7] p27 [vpp] reset v dd gnd osco osci [ce] p14 [a10] p12/halfho [a9] p11/ad1 [a8] p10/ad0 p20 [db0] p07/hsynco [a7] p31/scl [a13] dac4 [mode0] dac3 [pgm] hsynci vsynci/intv/ [a14] NT68P61A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p15 [a11] p13/halfhi p16/inte 17 18 19 20 24 23 22 21 dac5 [mode1] dac6 [mode2] dac7 p21 [db1] p22 [db2] p06/vsynco [a6] p05/dac13 [a5] p04/dac12 [a4] p03/dac11 [a3] p02/dac10 [a2] p01/dac9 [a1] p00/dac8 [a0] p30/sda [a12] [db6] p26 [db5] p25 [db4] p24 [db3] p23 * [ ]: otp mode [oe] dac2 dac1 dac0 [vpp] reset v dd nc gnd osco osci p15 [a11] p13/halfhi [a9] p11/ad1 [a8] p10/ad0 p00/dac8 [a0] p16/inte p01/dac9 [a1] p02/dac10 [a2] p03/dac11 [a3] p04/dac12 [a4] p06/vsynco [a6] p07/hsynco [a7] dac6 [mode2] nc dac5 [mode1] dac4 [mode0] dac3 [pgm] hsynci vsynci/intv dac7 [a14] NT68P61Au 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 [ce] p14 [a10] p12/halfho [db7] p27 [db6]p26 [db5] p25 [db4] p24 [db3] p23 17 18 19 20 21 p05/dac13 [a5] p31/scl [a13] p30/sda [a12] p20 [db0] p21 [db1] p22 [db2] 26 25 24 23 22 * [ ]: otp mode block diagram timing generator cpu core 6502 interrupt controller h/v sync signals processor sram + stack 256 bytes watch dog timer pwm dacs i/o ports osci osco v dd gnd hsynci inte scl sda dac0 - dac7 p00 - p07 p10 - p15 p20 - p27 vsynco a/d converter ad0 - ad1 8 bit base timer p30 - p31 iic bus p16 hsynco halfhi halfho dac8 - dac13 vsynci/intv otp program rom 24k bytes lvrc
NT68P61A 3 pin descriptions pin no. designation reset init. i/o description 40 pin 42 pin 1 1 dac2 [ oe ] o [ i ] open drain 12v, d/a converter output 2 [otp rom program output enable] 2 2 dac1 o open drain 12v, d/a converter output 1 3 3 dac0 o open drain 12v, d/a converter output 0 44 reset [ vpp ] i [ p ] schmitt trigger input pin, low active reset** [opt rom program supply voltage] 55 v dd ppower 6 7 gnd p ground 7 8 osco o crystal osc output 8 9 osci i crystal osc input 9 10 p15 i/o bi-directional i/o pin 10 11 p14 [ ce ] i/o [ i ] bi- directional i/o pin [otp rom program chip enable] 11 12 p13/halfhi [ a11 ] p13 i/o [ i ] bi- directional i/o pin, shared with half hsync i nput [otp rom program address buffer] 12 13 p12/halfho [ a10 ] p12 i/o [ i ] bi- directional i/o pin, shared with half hsync output [otp rom program address buffer] 13 14 p11/ad1 [ a9 ] p11 i/o [ i ] bi- directional i/o pin, shared with a/d converter c hannel 1 input [otp rom program address buffer] 14 15 p10/ad0 [ a8 ] p10 i/o [ i ] bi- directional i/o pin, shared with a/d converter channel 0 input [otp rom program address buffer] 15 16 p16/inte p16 i schmitt trigger input pin with internal pull high, shared with external rising-edge trigger interrupt 16 - 23 17 - 24 p27 - p20 [ db7 ] - [ db0 ] i/o [ i/o ] bi- directional i/o pin, push-pull structure with high current drive/sink capab ility [otp rom program data buffer] 24 25 p30/sda [ a12 ] p30 i/o [ i ] open drain 5v bi-direction i/o pin p30, shared with sda pin of i 2 c bus schmitt trigger buffer [otp rom program address buffer] 25 26 p31/scl [ a13 ] p31 i/o [ i ] open drain 5v bi-direction i/o pin p31, shared with scl pin of i 2 c bus schmitt trigger buffer [otp rom program address buffer] 26 27 p00/dac8 [ a0 ] p00 i/o [ i ] bi- directional i/o pin, shared with open drain 5v d/a converter output 8 [otp rom program address buffer] * [ ]: otp mode ** this reset pin must be pulled high by external pulled-up resistor (5k w suggestion), or it w ill stay low voltage to reset system all the time.
NT68P61A 4 pin descriptions (continued) pin no. designation reset init. i/o description 40 pin 42 pin 27 28 p01/dac9 [ a1 ] p01 i/o [ i ] bi- directional i/o pin, shared with open drain 5v d/a converter output 9 [otp rom program address buffer] 28 29 p02/dac10 [ a2 ] p02 i/o [ i ] bi- directional i/o pin, shared with open drain 5v d/a converter output 10 [otp rom program address buffer] 29 30 p03/dac11 [ a3 ] p03 i/o [ i ] bi- directional i/o pin, shared with open drain 5v d/a converter output 11 [otp rom program address buffer] 30 31 p04/dac12 [ a4 ] p04 i/o [ i ] bi- directional i/o pin, shared with open drain 5v d/a converter output 12 [otp rom program address buffer] 31 32 p05/dac13 [ a5 ] p05 i/o [ i ] bi- directional i/o pin, shared with open drain 5v d/a converter output 13 [otp rom program address buffer] 32 33 p06/vsynco [ a6 ] p06 i/o [ i ] bi- directional i/o pin, shared with vsync out [otp rom program address buffer] 33 34 p07/hsynco [ a7 ] p07 i/o [ i ] bi-directional i/o pin, shared with hsync out [otp rom program address buffer] 34 35 dac7 [ a14 ] o open drain 12v, d/a converter output [otp rom program address buffer] 35 36 dac6 [ mode2 ] o [ i ] open drain 12v, d/a converter output [otp rom mode select] 36 38 dac5 [ mode1 ] o [ i ] open drain 12v, d/a converter output [otp rom mode select] 37 39 dac4 [ mode0 ] o [ i ] open drain 12v, d/a converter output [otp rom mode select] 38 40 dac3 [ pgm ] o [ i ] open drain 12v, d/a converter output [otp rom program control] 39 41 hsynci i debouncing & schmitt trigger input pin for video horizontal sync signal, internal pull high, shared with composite sync input 40 42 vsynci/intv [a14] vsynci i [ i ] debouncing & schmitt trigger input pin for video vertical sync signal, internal pull high, shared with external interrupt source - 6 nc i/o bi-directional i/o pin, with internal pulled up 22k w resister, only 42 pin sdip available - 37 nc i/o bi-directional i/o pin, with internal pulled up 22k w resister, only 42 pin sdip available * [ ]: otp mode
NT68P61A 5 functional d escriptions 1. 6502 cpu the 6502 is an 8-bit cpu that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capab ility, programmable stack pointer with variable length stack, a wide selection of addressable memory, and interrupt input options. the cpu clock cycle is 4mhz (8mhz system clock divided by 2). refer to 6502 data sheet for more details. accumulator a index register y 0 7 7 index register x 70 0 stack pointer sp 0 n status register p 0 7 carry zero irq disable decimal mode brk command overflow negative 7 program counter pch 8 15 70 pcl 1 = true 1 = result zero 1 = disable 1 = true 1 = neg 1 = true 1 = brk vbdiz c figure 1. 6502 cpu registers and status flags
NT68P61A 6 2. instruction set list instruction code meaning operation adc add with carry a + m + c ? a, c and logical and a m ? a asl shift left one bit c ? m7 m0 ? 0 bcc branch if carry clears branch on c = 0 bcs branch if carry sets branch on c = 1 beq branch if equal to zero branch on z = 1 bit bit test a m, m7 ? n, m6 ? v bmi branch if minus branch on n = 1 bne branch if not equal to zero branch on z = 0 bpl branch if plus branch on n = 0 brk break forced interrupt pc+2 pc bvc branch if overflow clears branch on v = 0 bvs branch if overflow sets branch on v = 1 clc clear carry 0 ? c cld clear decimal mode 0 ? d cli clear interrupt disable bit 0 ? j clv clear overflow 0 ? v cmp compare accumulator to memory a - m cpx compare with index register x x - m cpy compare with index register y y - m dec decrement memory by one m - 1 ? m dex decrement index x by one x - 1 ? x dey decrement index y by one y - 1 ? y eor logical exclusive-or a ? m ? a inc increment memory by one m + 1 ? m inx increment index x by one x + 1 ? x iny increment index y by one y + 1 ? y
NT68P61A 7 instruction set list (continued) instruction code meaning operation jmp jump to new location (pc+1) ? pcl, (pc+2) ? pch jsr jump to subroutine pc + 2 , (p+1) ? pcl, (pc+2) ? pch lda load accumulator with memory m ? a ldx load index register x with memory m ? x ldy load index register y with memory m ? y lsr shift right one bit 0 ? m7 m0 ? c nop no operation no operation (2 cycles) ora logical or a + m ? a pha push accumulator on stack a php push status register on stack p pla pull accumulator from stack a - plp pull status register from stack p - rol rotate left through carry c ? m7 m0 ? c ror rotate right through carry c ? m7 m0 ? c rti return from interrupt p - , pc - rts return from subroutine pc - , pc+1 ? pc sbc subtract with borrow a - m - c ? a, c sec set carry 1 ? c sed set decimal mode 1 ? d sei set interrupt disable status 1 ? j sta store accumulator in memory a ? m stx store index register x in memory x ? m sty store index register y in memory y ? m tax transfer accumulator to index x a ? x tay transfer accumulator to index y a ? y tsx transfer stack pointer to index x s ? x txa transfer index x to accumulator x ? a txs transfer index x to stack pointer x ? s tya transfer index y to accumulator y ? a * refer to 6502 programming data book for more details.
NT68P61A 8 3. otp rom: 24k x 8 bits the otp rom storing application program code, executed by 6502 cpu, has a capacity of 24k x 8 bits, addressed from $a000 to $ffff. it is programmed by the universal eprom writer through a conversion adapter. in programming mode, otp rom is integrated with system and cannot be directly accessed. when using the otp rom alone, first enter the programming mode by setting: reset = vpp. at this time, through multiplex pins, normal procedures are used to program and verify the otp rom block with the universal programmer. otp rom mega cell d.c. electrical characteristics (read mode) (v dd = 5v , t a = 25 c, unless otherwise specified) symbol parameter min. typ. max. unit test conditions note v ih v dd -0.3 v dd +0.3 v1 v il input voltage -0.3 0.3 v 1 i il input current +/-10 m a i oh -400 m a v dd =5v, v oh = 4.5v i ol output voltage 1 m a v dd =5v, v ol = 0.5v i dd operating current 1 m a f = 4mhz 2 istb1 standby current 100 m a 3 notes: 1. all inputs and outputs are cmos compatible 2. f = 4mhz, iout = 0ma, ce = v ih , v dd = 5v 3. ce = v ih , oe = v il , v dd = 5v otp rom mega cell l a.c. electrical characteristics (read mode) (v dd = 5v, t a = 25 c, unless otherwise specified) symbol parameter min. max. unit conditions tcyc cycle time 250 ns t12 nonoverlap time to ph1 & ph2 5 65 ns tacc address access time 145 ns tce otpce to output valid 145 ns 4.5v < v dd < 5.5v tst output data setup time 20 ns toh output data hold time 0 ns otp rom mega cell a.c. test conditions output load 1 cmos gate and cl = 10pf input pulse rise and fall times 10ns max. input pulse levels 0v to 5v timing measurement reference level inputs 0v and 5v outputs 0.3v and 4.7v
NT68P61A 9 otp rom mega cell timing waveforms (read mode) tcyc t12 tacc & tce tst toh ph1 ph2 a0 - a14 otpce db0 - db7 otp rom mega cell a.c. electrical characteristics (programming mode) (t a = 25 c, unless otherwise specified) symbol parameter min. typ. max. unit test conditions note v dd supply voltage 6 6.5 v 4 vpp 10.5 12.75 v v ih input voltage 2 v dd +0.3 v v il -0.3 0.8 v iil input current +/-10 m a i oh output current -400 m a v dd = 5v, v oh = 4.5v i ol 1ma v dd = 5v, v ol = 0.5v i dd programming 30 ma ipp current 20 ma vpp = 12.75v note: 4. for reliability concern, we s uggested v dd = 6v & vpp = 12.75v for test otp rom ac characteristics in programming mode, using the same condition for the universal programmer supply voltage.
NT68P61A 10 otp rom mega cell d.c. electrical characteristics (programming mode) (t a = 25 c, unless otherwise specified) symbol parameter min. typ. max. unit test conditions note tms mode decode setup time 2 m s tmh mode decode hold time 2 m s tas address setup time 2 m s tah address hold time 2 m s tces ce setup time 2 m s tceh ce hold time 2 m s tds data setup time 2 m s tdh data hold time 2 m s tvs vpp setup time 2 m s tpw program pulse width 100 m s tdv oe to output valid 150 n s tdf oe to output in high-z 90 n s ce = v il otp rom mega cell a.c. test conditions output load 1 ttl gate and cl = 100pf input pulse rise and fall times 10ns max. input pulse levels 0.45v to 2.4v timing measurement reference level inputs 0.8v and 2.2v outputs 0.8v and 2.4v note: 5. v dd must be applied simultaneously or before vpp and cut off simultaneously or after v pp . 6. removing the device from power or setting the device with v pp = 12.75v may cause permanent damage to the device.
NT68P61A 11 otp rom mega cell timing waveforms (program mode) a0 - a14 db0 - db7 ce oe pgm vpp mode dec. test = vpp, mode [0..2] = 000; d in dout tms tmh tds tpw tdh tdv tdf tvs tas tces tceh tah
NT68P61A 12 otp rom mega cell mode selection reset = 12.75v, osci = v il , p16 = v ih , dac0 = v il mode [0..2] mode ce oe vpp db0 - db7 not vpp - - - normal operating - - - - vpp 000 output disable - v ih - high-z vpp 000 program v ih v ih vpp data in vpp 000 program verify v ih v il vpp data out vpp 000 program inhibit (standby) v il - vpp high-z vpp 001 security (program) v ih - vpp data in vpp 010 word-line stress - - vpp - vpp 011 bit-line stress - - vpp "0" vpp 100 otp row (after pkg) v ih v ih vpp data in vpp 101 otp column (after pkg) v ih v ih vpp data in * the security byte is at address $0000. read NT68P61A's otp rom mega cell has 2 control pins. ce (chip enable) controls the operation power and is used for device selection. the oe (output enable) controls the output buffers. output disable if oe = v ih , the outputs will be in a high impe dance state. two or more roms can be connected together on a common bus. standby by applying a low power level to the ce input, the chip enters standby reducing the operating current to 100 m a. program initially, all bits are in "1" state which is the erased state. the program operation is to introduce "0" data into the desired bit locations by electrical programming. when the vpp input is at 12.75v and ce is at v ih , the chip enters the programming mode. program verify the verify mode is to check if the desired data is correctly programmed on the programmed bit. the verify is accomplished with ce at v ih , vpp input is at 12.75v, and oe = v il . program inhibit using this mode, programming of two or more otp roms in parallel with different data is accomplished. all inputs except for ce and oe may be commonly connected, and a ttl high level program pulse is applied to the ce of the desired device only and ttl high level signal is applied to the other devices.
NT68P61A 13 4. ram: 256 x 8 bits 256 x 8-bit sram is used for data memory and stack. the ram addressing range is from $0080 to $017f. from $0100 to $017f is used as the edid data buffer when activating ddc1/2b mode transmission. the contents of ram are undetermined at power-up and are not affected by system reset. software programmers can allocate stack area in the ram by setting stack pointer register s. because the 6502 default stack pointer is $01ff, programmers must set register s to ffh when starting the program, so the stack area will map $01ff - $0180 to $00ff - $0080. as; ldx #$ff txs ram unused $0000 $0080 $0100 $00ff $a000 $ffff stack pointer $fffe $fffd $fffc rst-l rst-h irq-l irq-h reset vector irq vector $017f edid $0180 (24k bytes) otp rom $0025 system re g isters unused $bfff
NT68P61A 14 5. system registers addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0000 pt0 ffh p07 p06 p05 p04 p03 p02 p01 p00 rw $0001 pt1 7fh - p16 p15 p14 p13 p12 p11 p10 rw $0002 pt2dir ffh p27oe p26oe p25oe p24oe p23oe p22oe p21oe p20oe w $0003 pt2 ffh p27 p26 p25 p24 p23 p22 p21 p20 rw $0004 pt3 03h - - - - - - p31 p30 rw $0005 md con 07h - - - - - - - - - insen - hsel s/ c s/ c md1/ 2 md1/ 2 r w $0006 hv con 2fh hcntov vcntov hsynci vsynci hpoli vpoli hpolo vpolo r w $0007 hcnt l 00h hcl7 hcl6 hcl5 hcl4 hcl3 hcl2 hcl1 hcl0 r $0008 hcnt h 00h - - - - hch3 hch2 hch1 hch0 r $0009 vcnt l 00h vcl7 vcl6 vcl5 vcl4 vcl3 vcl2 vcl1 vcl0 r $000a vcnt h 00h - - - - vch3 vch2 vch1 vch0 r $000b syncon ffh nohalf enhalf - frun frfreq halfpol enh env w $000c endac ffh enad1 enad0 endk13 endk12 endk11 endk10 endk9 endk8 w $000d ad0 reg c0h cend csta ad05 ad04 ad03 ad02 ad01 ad00 r w $000e ad1 reg 00h - - ad15 ad14 ad13 ad12 ad11 ad10 r $000f iex 00h - - ieints ieintd ieinta ieintr ieinte ieintv w
NT68P61A 15 system registers (continued) addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0010 irqx 00h - - irqints irqintd irqinta irqintr irqinte irqintv r $0011 clr flg 00h clrhov clrvov clrints clrintd clrinta clrintr clrinte clrintv w $0012 clr wdt - 01010101w $0013 ii adr ffh ar7 ar6 ar5 ar4 ar3 ar2 ar1 - w $0014 ii dat 00h sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rw $0015 ii sts 08h - - start start stop stop enddc trx rxak - r w $0016 bt 00h bt7 bt6 bt5 bt4 bt3 bt2 bt1 bt0 w $0017 bt con 03h ------tbs enbt w $0018 dach0 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0019 dach1 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001a dach2 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001b dach3 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001c dach4 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001d dach5 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001e dach6 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001f dach7 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0020 dach8 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0021 dach9 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0022 dach10 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0023 dach11 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0024 dach12 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0025 dach13 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw note: the line above a writable signal name indicate an active low signal the dash line in these control register indicate an undefined bit the address of control register from $0026 to $007f are not used.
NT68P61A 16 6. timing generator this block generates the system timing and control signal to be supplied to the cpu and on-chip peripherals. a crystal quartz, ceramic resonator, or an external clock signal provided to the osci pin generates 8mhz system clock, (4 mhz for cpu), although internal circuits have a feedback resistor and capacitor included, components may be externally added to ensure proper operation. the typical clock frequency is 8mhz. this frequency w ill affect the operation of on-chip peripherals whose operating frequency is based on the system clock . 8mhz osci osco NT68P61A osci NT68P61A (1) (2) unconnected external clock osco figure 2. oscillator c onnections 7. a/d converter the analog to digital converter is a single 6-bit successive approximation converter. analog voltage is supplied from external sources to the a/d input pins and the results of the conversion are stored in the 6-bit data latch registers ($000d & $000e). the a/d converter is controlled by the control bits in the a/d control register endac. refer to the a/d channel format table a/d input pins activation. a conversion is started by setting a '0' to the conversion start bit ( csta ) in the a/d control register ($000d). this automatically sets the conversion end bit ( cend ) to '1'. when a conversion has been finished, cend bit automatically clears to '0'. the a/d conversion data in the ad latch registers ($000d & $000e) is valid digital data. the analog voltage to be measured should be stable during the conversion operation. the variation should exceed 1/2 lsb for accuracy in measurement. please refer figure 3 for checking the linearity of a/d. a/d channel format table enad1 enad0 p11 line p10 line 00ad1ad0 01ad1p10 10p11ad0 11p11p10
NT68P61A 17 a/d channel control register addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $000c endac ffh enad1 enad0 endk13 endk12 endk11 endk10 endk9 endk8 w $000d ad0 reg c0h cend csta ad05 ad04 ad03 ad02 ad01 ad00 r w $000e ad1 reg 00h - - ad15 ad14 ad13 ad12 ad11 ad10 r input voltage digital value input voltage digital value input voltage digital value 0.12 0 ($00) 1.79 23 ($17) 3.5 46 ($2e) 0.37 1 ($01) 2.03 27 ($1b) 3.75 49 ($31) 0.53 7 ($07) 2.27 30 ($1e) 3.99 52 ($34) 0.78 10 ($0a) 2.51 33 ($21) 4.22 56 ($38) 1 14 ($0e) 2.76 36 ($24) 4.46 63 ($3f) 1.28 17 ($11) 3 40 ($28) 4.7 63 ($3f) 1.54 20 ($14) 3.25 43 ($2b) 4.95 63 ($3f) input voltage digital value 0 0.2 0.4 0.6 0.8 1 0 10 20 30 40 50 60 70 linear range 0.3 0.7 these digitals have 1 lsb deviation v dd figure 3. a/d converter linearity diagram
NT68P61A 18 8. pwm dacs (pulse width modulation d/a converters) there are 14 pwm d/a converters with 8-bit resolution in NT68P61A. eight of these d/a (dac0 - dac7) converters are open-drain output structures with 12v applied (maximum), and the other six d/a converters (dac8 - dac13) are open-drain output structures with 5v applied (maximum). the pwm frequency is 31.25 khz on 8 mhz system clock. use of a different oscillator frequency will result in different pwm frequency. as dac8 - dac13 are shared with i/o port pins, user can write '0' to corresponding enable bit in the endac control register to activate each of dach8 - 13. there are 14- channel readable dach registers corresponding to 14 d/a converters. each pwm output pulse width is programmable by setting the 8 bit digital to the corresponding dach registers. when these dach registers are set to 00h, the dac will output low (gnd level) and each bit addition w ill add 125ns pulse width. after reset, all dac outputs are set to 80h (1/2 duty output). refer to figure 4 for the detailed timing diagram of pwm d/a output. 01 02 m 255 (ff) 8mhz fosc 255 0 1 2 m m+1 m+2 255 0 1 pwm value: 00 figure 4. the dac output timing diagram and wave table dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 dac output duty cycle 00000000 gnd 0 0 0 0 0 0 0 1 1/256 vref. 0 0 0 0 0 0 1 0 2/256 vref. 0 0 0 0 0 0 1 1 3/256 vref. 0 0 0 0 0 1 0 0 4/256 vref. - - - - - - - - - - - - - - - - - - - - - - - - x /256 vref. 1 1 1 1 1 1 1 0 254/256 vref. 1 1 1 1 1 1 1 1 255/256 vref. the dac value correspondent to pwm output * vref. is 12v or 5v
NT68P61A 19 addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $000c endac ffh enad1 enad0 endk13 endk12 endk11 endk10 endk9 endk8 w $0018 dach0 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0019 dach1 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001a dach2 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001b dach3 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001c dach4 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001d dach5 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001e dach6 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $001f dach7 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0020 dach8 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0021 dach9 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0022 dach10 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0023 dach11 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0024 dach12 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw $0025 dach13 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw dac control register ($000c) and dac value register ($0018 - $0025) control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $000c endac ffh enad1 enad0 endk13 endk12 endk11 endk10 endk9 endk8 w $0018 dach0 80h dkvl7 dkvl6 dkvl5 dkvl4 dkvl3 dkvl2 dkvl1 dkvl0 rw endk8 : enable dac channel 8; when clearing this bit to '0', the i/o port, p00, will c hange to dac channel 8. when setting this bit to '1', the i/o port will restore to p00. endk9 - endk13 : the manipulation is the same as endk8 bit, and control dac channel 9 - 13. dach0 (dkvl0 - dkvl7): setting dac output waveform of dac channel 8. please check figure 3 for the timing diagram and wave table. dach1 - dach13: the manipulation is the same as dach0 register, and control dac channel 1 - 13.
NT68P61A 20 9. reset NT68P61A can be reset by the external reset pin or by the internal watch-dog timer. this resets or starts the microcontroller from a power-down condition. during the time that this reset pin is held low (*reset line must be held low for at least two cpu clock cycles), writing to or from the m c is inhibited. when positive edge is detected on the reset input, the m c will immediately begin reset sequence. after a system initialization time of six cpu clock cycles, the mask interrupt flag will be set and the m c will l oad the program counter from the memory vector locations $fffc and $fffd. this is the start location for program control. to improve noise immunity a schmitt trigger buffer is provided at the reset . reset status is as follows: 1. port0 port1. port2. port3 pins will act as i/o ports with high output. 2. sync processor counters reset and vcnt | hcnt latches cleared 3. all sync outputs are disabled 4. base timer is disabled and cleared 5. a/d converter is disabled and stopped 6. ddc1/2b function is disabled 7. pwm dac0 - dac7 output 50% duty waveform and dac8 - dac13 is disabled 8. watch-dog timer is cleared and enabled this reset pin must be pulled high by external pulled- up resistor (5k w suggestion), or it w ill stay low voltage to reset system all the time. 10. watch-dog timer (wdt) and low voltage reset circuit (lvrc) NT68P61A implements a watch-dog timer reset to avoid system shut-down or malfunction. the clock of the wdt is from on-chip rc oscillator not requiring any external components. the wdt runs regardless if the clock of the osci/osco pins of the device has been st opped. the wdt time interval is about 0.5 second. the wdt must be cleared within every 0.5 second when software is in normal sequence, otherwise the wdt will overflow and cause reset. the wdt is cleared and enabled after system is reset. it cannot be disabled by software. users can clear the wdt by writing 55h to clrwdt register. NT68P61A will check voltage level of power s upply. when the voltage level of power supply is below a threshold of 4.0v, the lvrc will issue a reset output to the chip. after the power supply is restored to 4.0v and above, the lvrc w ill keep reset si gnal low for 10ms and then restore to high voltage. a power glitch of pulse width less than 1 m s will be i gnored and no reset will occur. this allows the m c enter the reset state in a good condition. refer to figure 5 for the timing diagram. as; lda #$55 sta $0012 addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0012 clr wdt - 0 1 0 1 0 1 0 1 w vcc = 5.0 v 4.0 v hold 10 ms s y stem reset gnd figure 5. lvr reset timing diagram
NT68P61A 21 11. interrupt controller the m c will complete the current instruction being executed before recognizing the interrupt request. at this time, the interrupt mask bit in the status register will be examined. if the interrupt mask bit is not set, m c will begin interrupt sequence. the program counter and processor status register are stored in the stack. m c will then set the interrupt mask flag high so that no further interrupts occur. at the end of this cycle, the program counter w ill be l oaded from addresses $fffe & $ffff, transferring program control to the memory vector located at these addresses. six interrupt sources are available in this system: - intv int (vsync int): rising edge of every vsync pulse - inte int (external int): rising edge of external interrupt pulse - intmr int (timer int): as the base timer counter overflow and counting from $ff to $00 - inta int (address matched int): external device calling NT68P61A in ddc2 mode communication - intd int (shift register int): shift register is empty or receiving a new byte data in ddc1 & ddc2 mode communication - ints int (scl go-low int): external device proceed a ddc2 communication three memory mapped registers are used to control the interrupt operation. the irqx is set by the rising edge of external pins (intv & inte), base timer overflow (intr), scl line go-low (ints), and serial bus interrupt (inta & intd). the serial bus interrupt is generated by the i 2 c circuit as described in under i 2 c bus interface sections. the interrupt enable (iex) bit w ill effects the interrupt process if the irqx has already been set. once iex bit is set, its corresponding interrupt w ill generate an interrupt source for 6502 cpu. the irqx w ill be set no matter the iex bit enable or not. the interrupt request is generated when irqx and iex are both '1'. the irqx remains in high state unless the clrirq register is cleared (write '1' to correspondent bit in clrirq register). the interrupt enable register (iex) and interrupt request register (irqx) are memory mapped registers which can only be accessed or tested by program. these registers are cleared to '0' at initialization after the chip is reset . when interrupt occurs, cpu jumps to $fffe & $ffff to execute interrupt service routine and finds which one of the interrupt sources is active by checking the irqx. upon entering the interrupt service routine, the irqx that caused the interrupt service must be cleared in the interrupt service routine program. cpu clears irqx by writing '1' to the corresponding bit in clrirq register. if more than one interrupt is pending and waiting to be served, each is executed by priority. priority is defined by the programmer. control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $000f iex 00h - - ieints ieintd ieinta ieintr ieinte ieintv w $0010 irqx 00h - - irqints irqintd irqinta irqintr irqinte irqintv r $0011 clr flg 00h clrhov clrvov clrints clrintd clrinta clrintr clrinte clrintv w irqints is the interrupt flag for scl- at ddc2b transmission mode, it is set when scl line changes from '1' to '0'. ieints enable 6502 interrupt for ints. - when this bit is set to '1' and irqints flag is set, 6502 w ill accept interrupt source and jump to interrupt service routine assigned by interrupt vector. clrints clears ints interrupt flag. - before returning from interrupt service routine, this flag must be cleared. the manipulation of other interrupt source is the same as ints. clrhov & clrvov: clear the overflow flag of h/v counter and reset h/v counter to zero.
NT68P61A 22 12. i/o ports NT68P61A has 25 pins dedicated to input and output. these pins are grouped into 4 ports . 12.1. port0: p00 - p07 port0 is an 8-bit bi-directional cmos i/o port with pmos as internal pull-up (figure 6). each pin of port0 may be bit programmed as an input or output port without the software controlling the data direction register. when port0 works as output, the data to be output is latched to the port data register and output to the pin. port0 pins that have '1's written to them are pulled high by the internal pmos pull-ups. in this state they can be used as input, then the input signal can be read. this port outputs high after reset . p00 - p05 are shared with dac8 - dac13 respectively. if user sets endk8 - endk13 low in endac register, p00 - p05 will act as dac8 - dac13 respectively (figure 7). after the chip is reset, endk - endk13 will enter high state and p00 - p05s w ill act as i/o ports. p06, p07 are shared with vsynco & hsynco respectively. if user sets enh , env to low in syncon register, p06, p07 will act as vsynco & hsynco respectively (figure 8). after the chip is reset, enh , env , will enter high state and p06, bp07 w ill act as i/o pins. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0000 pt0 ffh p07 p06 p05 p04 p03 p02 p01 p00 r w $000b syncon ffh nohalf enhalf - frun frfreq halfpol enh env w $000c endac ffh enad1 enad0 endk13 endk12 endk11 endk10 endk9 endk8 w vcc i/o data out data in figure 6. i/o structure pwm output pwm data in figure 7. pwm output structure vcc o/p data out
NT68P61A 23 figure 8. output structure
NT68P61A 24 12.2. port1: p10 - p16 port10-port15 are 6-bit bi-directional cmos i/o ports with pmos as the internal pull-up (figure 6). port16 is an input pin only. each bi-directional i/o pin may be bit programmed as an input or output port without software controlling the data direction register. when port1 works as output, the data to be output is latched to the port data register and output to the pin. port1 pins that have '1's written to them are pulled high after reset. p10, p11 are shared with ad0 & ad1 input pins respectively. if user clears the enadx bit in the endac control register to low, a/d converters will activate simultaneously. after the chip is reset, enadx bits enter high state and p10, p11 act as i/o pins. p12, p13 are shared with half signals input and output pins by accessing syncon control register. if user clears the enhalf bit to low, p13 will switch to halfhi pin (input pin) and p12 w ill switch to halfho pin (output pin, figure 8). refer to half frequency function in the h/v sync processor paragraph concerning halfhi & halfho pin. after the chip is reset, the enhalf bits will enter high state and p12, p13 w ill act as i/o pins. p16 has a schmitt trigger input buffer (figure 9) and is shared with the external interrupt pin if set the ieinte bit in iex control register. refer to 'interrupt controller' section above for function details. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0001 pt1 7fh - p16 p15 p14 p13 p12 p11 p10 rw $000c endac ffh enad1 enad0 endk13 endk12 endk11 endk10 endk9 endk8 w $000d ad0 reg c0h cend csta ad05 ad04 ad03 ad02 ad01 ad00 r w $000e ad1 reg 00h - - ad15 ad14 ad13 ad12 ad11 ad10 r $000f iex 00h - - ieints ieintd ieinta ieintr ieinte ieintv w data input i/p vcc figure 9. schmitt input structure vcc i/o data out . data oe data in figure 10. i/o structure
NT68P61A 25 12.3. port2: p20 - p27 port2, an 8-bit bi-directional i/o port (figure 10), which may be programmed as an i nput or output pin by the software control. when setting the pt2dir control bit to '0', its corresponding pin w ill act as output pin. clearing pt2dir bit to '1', acts as an input pin. when programmed as an input, it has an internal pull-up resistor. when programmed as an output, the data to be output is latched to the port data register and output to the pin with push-pull structure. if programmed as an output pin, user can read out its correspondent control bit about what user has written before. if programmed as an input pin, user can read out what the i/o pin status outside. this port acts as an i nput port after reset. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0002 pt2dir ffh p27oe p26oe p25oe p24oe p23oe p22oe p21oe p20oe w $0003 pt2 ffh p27 p26 p25 p24 p23 p22 p21 p20 rw 12.4. port3: p30 - p31 port3 is an 2 bit bi-directional open-drain i/o port (figure 11). each pin of port3 may be bit programmed as an i nput or output pin with open drain structure. when port3 works as an output, the data to be output is latched to the port data register and output to the pin. for port3 pins that have '1's written to them, user must connect port3 with external pulled- up resistor and then port3 can be used as input (the input signal can be read). this port outputs high after reset . p30, bp3 include schmitt trigger buffer for noise immunity and can be configured as the i 2 c pins sda & scl respectively. if set enddc to low in iists control register, p30, p31 will act as sda, scl respectively. after the chip is reset, enddc will be in high and port3 w ill act as i/o pins. addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0004 pt3 03h - - - - - - p31 p30 rw $0015 ii sts 0fh - - start start stop stop enddc trx rxak r w i/o data out data in figure 11. open drain i/o structure
NT68P61A 26 13. h/v sync signals processor the functions of the sync processor include polarity detection, hsync & vsync signals counting, programmable sync signals output, free running signal generator and composite sync separation. the processor properly handles either composite or separate sync signal inputs as well as no sync signal input. the input at hsynci can be either a pure horizontal sync signal or a composite sync signal. for the sync waveform refer to figures 12 and 13. the sync processor block diagram is shown in figure 17. both vsynci & hsynci pins have a schmitt trigger and filtering process to improve noise immunity. any pulse that is shorter than 125ns w ill be regarded as a glitch and w ill be i gnored. 13.1. v & h counter register: vcntl/h, hcntl/h vsync counter: vcntl/h, the 12-bit read only register, contains information of the vsync frequency. an internal counter counts the numbers of 8 m s pulse between two vsync pulses. when the next vsync signal is recognized, the counter is stopped and the vcnt register latches the counter value. the counted data can be converted to the time duration between two successive vsync pulses by 8 m s. if no vsync comes, the counter w ill overflow and set vcntov bit (in hvcon register) to high (see figure 14). once the vcntov sets to high, it keeps in high state unless cleared by clrvov bit (in clrflg register) to high. when user clears the clrvov bit, the vcnt counter w ill be reset to zero and begin to count again. hsync counter: hcntl/h, the other 12-bit read only register pairs contain the numbers of hsync pulse between two vsync pulses (see figure 15), and the data can be read to determine if the frequency is valid and to determine the video mode. if the hsel bit sets to high, the internal counter counts the hsync pulses between two vsync pulses. if the hsel bit clears to low, the internal counter w ill be reset and begin counting the hsync pulses in each 8.192ms interval (see figure 16). the counted value w ill be latched by the hcntl/h register pairs which are updated by every vsync pulse or 8.192ms interval. if the counter overflows, the hcntov bit (in hvcon register) w ill be set to high. once the hcntov sets to high, it remains in the overflow high state unless cleared by clrhov (in clrflg register) to high. when user clears the clrhov bit, the hcnt counter w ill be reset to zero. (a) positive polarity (b) negative polarity figure 12. separate h sync. waveform (a) positive polarity (b) negative polarity figure 13. composite h sync. waveform
NT68P61A 27 vsynci sampling clock 8 m s ? ? ? latch vcnt re g ister reset v sync. counter start pulse countin g latch vcnt re g ister reset v sync. counter start pulse countin g ? ? ? figure 14. vsync counter operation hsynci vsynci ? ? ? latch hcnt re g ister reset h sync. counter start pulse countin g latch hcnt re g ister reset h sync. counter start pulse countin g ? ? ? figure 15. hsync counter operation using vsync pulse hsynci ? ? ? hsel = low 8.192 ms ? ? ? latch hcnt re g ister reset h sync. counter start pulse countin g latch hcnt re g ister reset h sync. counter start pulse countin g figure 16. hsync counter operation using 8.192ms time interval
NT68P61A 28 enable enable enable enable reset reset 8 m s 8.192 ms hsel control logic v sync. latch h sync. latch sync separator h hpoli vpoli v h hpolo vpolo h & v sync. polarity detector h sync. output control free_run control vsync input hsync input hsynco 0 1 1 0 vsynco hcntl hcnth digital filter vcntl vcnth s/c v 0 1 v schmitt trigger digital filter schmitt trigger h sync. counter v sync. counter v sync. output control s/c figure 17. sync. processor block diagram
NT68P61A 29 13.2. sync processor control register: composite sync: user has to determine whether the incoming signal is separate sync or composite sync and set s/ c & hsel bit properly. if composite sync signal is input, after set s/ c to '0', the sync separator block will be activated ( please refer figure 18). during vsync pulse the hsync will be inserted hsync pulse by hardware circuit and the pulse width of inserted pulse is 2 m s fixed. according to the last hsync pulse outside the vsync pulse duration, the hardware will arr ange the interval of these hardware interpolated pulse. so the insertion of these hsync pulse will be continued inside the vsync pulse duration no matter what the hsync pulse originally exist or not. these inserted hsync pulse have 0.5 m s phase deviation maximum. the vsync pulse can be extracted by hardware from composite signal, and the output of vsync signal delay time w ill be limited bellow 20ns. for inserting hsync pulse safely, the extracted vsync pulse will be widen about 9 m s. because evenly putting the hsync pulse, the last inserted hsync pulse will have different frequency from original ones. system will not implement this insertion function, user must clear insen bit in the md_con control register to activate this function. after reset, the hsel , s/ c & insen bits default value is high and clear the vcnt | hcnt counter latches to zero. polarity: the detection of hsync or vsync polarity is achieved by hardware circuits sample the sync signal's voltage level periodically. the user can read hpoli & vpoli bit in hvcon register, from which bit = '1' representing positive polarity and '0', negative polarity. the user can read hsynci and vsynci bit in hvcon register to detect h & v sync input signal. the user can control the polarity of h & v sync output signal by writing the appropriate data to the hpolo and vpolo bits in the hvcon register, '1' represents positive polarity and '0', negative polarity. sync output: in pin assignment, vsynco & hsynco represent vsync & hsync output which are shared with p06 & p07 respectively. if set env & enh to '0' in syncon register, p06 & p07 will act as vsynco & hsynco pin. when input sync is separate signal, the v/hsynco will output the same si gnal as input sync signal without delay. but if input sync is composite signal, the vsynco signal w ill have a delay time of about 4 m s to 8 m s. the hsynco has no delay output and still has vsync pulse am ong hsync pulse (i.e. the signal on hsynci pin directly output to hsynco pin.) free run signal output: the user can set frun to '0' bit in syncon register, then vsynco will output 61hz vsync signal and hsynco w ill output 62.5khz hsync signal default (refer to figure 20). when frfreq bit clears to '0', the hsynco pin will output 41.7 khz hsync signal. the free run signal has negative or positive polarity depending on the hpolo & vpolo bit setting in the hv_con control register, '1' is positive and '0' is negative polarity. after chip reset, env , enh , frfreq & frun will enter high state and p06 & p07 w ill act as i/o pins. half frequency input and output: in this pin assignment, when enhalf sets to '0' in syncon register, the halfho pin will act as an output pin and output half of input signal in the halfhi pin with 50% duty (refer to figure 21). if nohalf sets to '0', halfho will output the same signal in the halfhi pin and user can control its polarity output of halfho by setting halfpol bit, '1' for positive and '0' for negative polarity. after chip reset, enhalf , nohalf & halfpol will be in the high state and p13 & p17 w ill act as i/o pins.
NT68P61A 30 ? ? ? composite h s y nc. waveform ( h eor v ) ( 1 ) hsynci ? ? ? ( 2 ) hsynci composite h s y nc. waveform ( h or v ) ? ? ? 2 m s no matter hsync pulse existing or not, the output signal of hsync will be inserted. hsynco inserted hsync pulse vsynco original hsync pulse original hsync pulse widen 9 m s figure 18. composite h & v sync. processing
NT68P61A 31 vcntov = '1' ? hcnth = '00' ? no yes yes no read vcnt|hcnt counter register normal mode seperate sync. freq. calculating set s/c = '0' clear vcntov & hcntov open intv & clear intv flag vcntov = '1' ? no yes yes no return stand-by mode off mode worng mode yes no suspend mode return freq. calculating 1. extract hcntl/h 12 bit data 2. 12 bit data * vsync. freq. = hsync. freq. 3. its reciprocal is hsync. time duration. 1. extract vcntl/h 12 bit data 2. hsel = '1' 12 bit data x 8 m s = vsync. time duration 3. its reciprocal is vsync. freq. 4. hsel = '0' 12 bit data x 8.192ms = vsync. freq. set s/c = '1' & hsel = '0' clear vcntov & hcntov delay 10ms normal mode composite sync. hcnth ='00' ? hcnth = '00' ? sync. mode processing intv ? no yes delay 60ms delay 31 ms read vcnt|hcnt counter register system default: open intv & clear intv flag s/c = '1' & hsel = '1' figure 19. h & v sync. software control flowchart (for reference only)
NT68P61A 32 (a) free run output vsync. signal 61hz (1) 62.5khz (2) 41.7khz pulse width 64 m s (b) option 2 of free run output hsync. signal pulse width 1 m s figure 20. free running sync. waveform halfhi halfho: half freq. output signal (50% duty) halfho output signal when nohalf bit clears to low (the same signal as in the halfhi pin) figure 21. half freq. sync. waveform
NT68P61A 33 13.3. power saving mode detect: the video mode is listed below. power saving is from mode 2 to mode 4. all modes can be detected by setting the control register properly. refer to figure 15 control flow chart for software reference. mode h-sync v-sync (1) normal active active (2) stand by inactive active (3) suspend active inactive (4) off inactive inactive control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0005 md con 07h - - - - - - - - - insen - hsel s/ c s/ c md1/ 2 md1/ 2 r w $0006 hv con 2fh hcntov vcntov hsynci vsynci hpoli vpoli hpolo vpolo r w $0007 hcnt l 00h hcl7 hcl6 hcl5 hcl4 hcl3 hcl2 hcl1 hcl0 r $0008 hcnt h 00h - - - - hch3 hch2 hch1 hch0 r $0009 vcnt l 00h vcl7 vcl6 vcl5 vcl4 vcl3 vcl2 vcl1 vcl0 r $000a vcnt h 00h - - - - vch3 vch2 vch1 vch0 r $000b syncon ffh nohalf enhalf - frun frfreq halfpol enh env w $0011 clr flg 00h clrhov clrvov clrints clrintd clrinta clrintr clrinte clrintv w mdcon control register: s/ c : the sync mode control. if the input of v & h sync are separate signals, set this bit to '1' (system default). if the input is composite signal, clear this bit. under the composite mode, NT68P61A will extract the v sync form h sync signal. hsel : when clearing this bit, system w ill reset hcntl|h counter to zero. the number of hsync pulse at the 8.192ms interval is obtained. insen : user can clear this bit for inserting hsync pulse when processing the composite signal. system will disable this function after reset. hvcon control register: hcntov: the overflow bit of h sync. after setting hsel bit '1' without any input vsync pulses and there are more than 4096 hsync pulses coming ,this bit will be set. it will keep '1' and user can clears it by setting clrhov bit to '1' at the clrflg control register. after cleared, the h sync counter w ill reset to '0' and start counting for every hsync pulse. vcntov: the overflow bit of v sync. the operation is the same as hcntov. after cleared, the vsync counter w ill reset to '0' and start counting for every 8 m s. hsynci & vsynci:user can instantaneously detect input of h & v sync pulse at any time. hpoli & vpoli: the polarity of input h & v sync pulse - '1' for positive polarity and '0' for negative polarity. hpolo & vpolo:to control the output polarity of h & v sync pulse - '1' for positive polarity and '0' for negative polarity. hcntl|h & vcntl|h control registers: the 12 bits counter for h & v sync pulse. syncon control register: enh & env : enable the output of h & v sync. the p06 & p07 will switch to vsynco & hsynco output. frun : open free run signal at the vsynco & hsynco output. frfreq : select the free run frequency of h sync output. enhalf : p12 & p13 will switch to halfho & halfhi pin. the halfho will output the half si gnal at the halfhi pin with 50% duty. nohalf : user must clear enhalf first. the halfho will output the same si gnal at the halfhi pin. halfpol: user must clear enhalf first and control the
NT68P61A 34 polarity at the halfho output pin - '1' for positive polarity and '0' for negative polarity . 14. base timer (bt) the base timer is an 8-bit counter whose clock source must be chosen with 1 m s or 1ms by setting or clearing the tbs bit ('0' for 1 m s and '1' for 1ms). the bt can be enabled/disabled by the enbt bit in the btcon register. when user clearing this control bit to '0', the bt will start c ounting, otherwise setting this bit to '1' w ill stop the c ounting. after chip is reset, the tbs and enbt bits are set to '1' (the bt is disabled). bt, can be preset by writing bt7 - bt0 to the bt register (write only) at any time and the bt w ill start c ount-up from preset value. when the value reaches ffh, it generates a timer interrupt if the timer interrupt is enabled. when it reaches the maximum value of ffh, the base timer w ill wrap ar ound and begin counting at 00h. the timer interval can be within 256 ms maximum if set tbs to '1'. the timer interval can be within 256 m s maximum if set tbs to '0'. bt7 tmr int 1 m s 1ms tbs 1 0 bt6 bt5 bt4 bt3 bt2 bt1 bt0 control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0016 bt 00h bt7 bt6 bt5 bt4 bt3 bt2 bt1 bt0 w $0017 bt con 03h ------tbs enbt w bt control register : bt0 - bt7: preloaded value of the base timer. the timer w ill c ount-up from this value. btcon control register: enbt : when clearing this bit, the base timer will be activated. tbs: select the input clock source of base timer - '1' for 1ms and '0' for 1 m s.
NT68P61A 35 15. i 2 c bus interface: ddc1 & ddc2b slave mode i 2 c bus interface is a two-wire, bi-directional serial bus which provides a simple, efficient way for data communication between devices. its structure minimizes the cost of connecting various peripheral devices. in short, the wired-and connection of all i 2 c interface to i 2 c bus is the most important structure. two modes of operation have been implemented in NT68P61A: uni-directional mode (ddc1 mode) and bi-directional mode (ddc2b mode). if the md1/ 2 bit is set to '1', the device will operate in the ddc1 mode, and if the md 1/ 2 bit is cleared to '0', the device will operate in the ddc2b mode. all of these i 2 c functions will be activated only when enddc bit clears to '0' (in iists register). when i 2 c bus function is activated, the p30 & p31 will switch to scl & sda pin. system works on the ddc1 mode transmission default. the scl pin will remain high and sda w ill transfer one bit of data at every rising edge of vsync pulse. shift register (iidat) clock source vsync sda scl md1/2 0 1 15.1. ddc1 bus interface vsync input and sda pin: in ddc1 data transfer, the vsync input pin is used as an input clock for data transmission and sda output pin, as serial data line. this function comprises of two data buffers: one is a preloaded data buffer for user placing one bit of data in advance, and one is shift register for system shifting out one bit of data to the sda pin. these two data buffer cooperate properly. refer to figure 18. after system reset, the i 2 c bus interface is in ddc1 mode. data transfer: in advance, put one byte transmitted data into iidat register and activate i 2 c bus by setting enddc bit to '0' and open intd interrupt source by setting ieintd to '1'. on the first 9 rising edge of vsync, system w ill shift out any invalid bit in shift register to sda pin to empty shift register. when shift register is empty and on next rising edge of vsync, it w ill l oad data in the iidat register to internal shift register. at the same time, NT68P61A will shift out msb bit and generate an intd interrupt to remind user to replace next byte data into iidat register. after eight rising clocks, there are eight bits shifted out in proper order and the shift register becomes empty again. at the ninth rising clock, it will shift the ninth bit (null bit '1') out to sda. and on the next rising edge of vsync clock, system w ill generate a intd interrupt again. NT68P61A w ill also l oad new data in the iidat register to internal shift register and shift out one bit immediately. user must input new data to iidat register properly before the shift register is empty (the next intd interrupt). vsync clock: in the separate sync signal, the vsync pulse is used as a data transfer clock. its frequency allows 25khz maximum. if no vsync input signal is found, NT68P61A can not transmit any data to sda pin regardless what the vsync has extracted from composite hsync signal.
NT68P61A 36 control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0005 md con 07h - - - - - - - - - insen - hsel s/ c s/ c md1/ 2 md1/ 2 r w $000f iex 00h - - ieints ieintd ieinta ieintr ieinte ieintv w $0010 irqx 00h - - irqints irqintd irqinta irqintr irqinte irqintv r $0011 clr flg 00h clrhov clrvov clrints clrintd clrinta clrintr clrinte clrintv w $0014 ii dat 00h sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rw $0015 ii sts 08h - - start start stop stop enddc trx rxak - txak r w mdcon control register: md1/ 2 : select the ddc mode - '1' for ddc1 and '0' for ddc2b mode. system w ill be ddc1 mode by default. when transmission mode is changed form ddc1 to ddc2b, system automatically clears this bit. iex control register: at ddc1 mode, only open intd interrupt, as well as open ints interrupt to detect if has changed to ddc2b mode. ii_dat control register: data buffer for transmission. ii_sts control register: enddc : when clearing this bit, system w ill activate ddc transmission. p30 & p31 w ill switch to sda & scl pin. 12 3 4 912 34 567 intv 8912 vsync pulse enddc (in iists register) intd 876 87654321 shift register sda 187 null bit 543 18 62 null bit ? ? ? 5 7 msb lsb second b y te data first b y te data invalid data user can load next b y te data to iidat re g ister load data in the iidat re g ister to shift re g ister ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? figure 22. ddc1 mode timing diagram
NT68P61A 37 15.2 ddc2b slave mode bus interface the ddc2b i 2 c bus interface features are as follows: - slave mode (NT68P61A addressed by a master which drive scl signal) - fully compatible with i 2 c bus standard - interrupt and generation of acknowledge handled by user for communication - interrupt driven byte by byte data transfer - calling address identification interrupt - detection of start and stop signals enable i 2 c and ints: the NT68P61A included the use in applications requiring storage and serial transmission of configuration and control information. user can place address data into iiadr register and set ieints to '1' (in iex register) in advance. in the ddc1 mode (after clearing enddc to '0') and when the low level on the scl pin occurs, NT68P61A will remind user by generating a ints interrupt and switch to ddc2b mode automatically. when user sets md1/ 2 to '1' at this time, the NT68P61A will still proceed with a ddc1 communication. the ddc2b bus consists of two wires, scl and sda; scl is for the data transmission clock and sda is for the data line. data transfers follow the format shown in figure 19. the standard communication of i 2 c bus protocol includes four parts: a start signal, slave address, transferred data (proceed byte by byte) and a stop signal. in the wired-and connection, any slow devices can hold the scl line low to force the fast device into a wait state until the slow device is ready for the next bit or byte transfer in a type of handshake procedure. 876 5 187 ack 543 18 62 ? ? ? 7 ? ? ? 1 - 7 scl 89 ? ? ? 1 - 7 89 ? ? ? 1 - 7 89 sda start condition stop condition address r/w ack data ack data ack 4 ? ? ? iidat reg. bit stream msb msb msb lsb lsb ack figure 23. ddc2b data transfer
NT68P61A 38 start condition: when scl & sda lines are in high state, an external device (master) may initiate communication by sending a start signal (defined as sda from high to low transition while scl is in high state). when there is a start condition, NT68P61A will set the 'start' bit to '1' and user can poll this status bit to control ddc2b transmission at any time. this bit will keep '1' until user clears it. after sending a start signal for ddc2b communication, an external device can repeatedly send start conditions without sending a stop signal to terminate this communication. this is used by the external device to communicate with another slave or with the same slave in different mode (read or write mode) without releasing the bus. address matched and inta: after the start condition, a slave address is sent by external device. when i 2 c bus interface changes to ddc2b mode, NT68P61A w ill first act as a receiver to receive this one byte data. this address data is 7 bits long followed by the eighth bit that indicates the data transfer direction (r/ w ). when NT68P61A system receives address data from external device, it will store if in iidat register. system s upport 'a0' address by default and another one set of ddc2 address for user. when user enable ddc2 function, the system w ill compare address data getting from external device with the default address 'a0' and data in the $0013 ii_adr control register written by user. either of these address matched, the system w ill generate an inta interrupt flag and this ddc2 communication w ill be continued. if user sets ieinta bit to '1' in advanced and address data matched, the NT68P61A system will generate a inta interrupt. under the address matching condition, the NT68P61A w ill send an acknowledgment to external device. if address data not matched, the NT68P61A will not generate inta interrupt and not care the data change on sda line in the future. data transmission direction: at inta interrupt servicing routine, user must check the lsb of address data in iidat register. according to i 2 c bus protocol, this bit indicates the ddc2b data transfer direction in later transmission - a '1' indicates a request for 'read mode' action (external read data from system); a '0' indicates a 'write mode' action (external write data to system). for read mode and write mode timing diagram refer to figure 24 and 25. the data transfer can be proceeded byte by byte in a direction specified by the r/ w bit after a successful slave address is received. user must set trx bit in the iists register for NT68P61A transmission mode - '1' for read mode and '0' for write mode. data validity and transfer: the data on the sda line mu be stable during the high period of the clock on the scl line. the high and low state of the sda line can only change when the clock signal on the scl line is low. each byte data is eight bits long and one clock pulse for one bit of data transfer. data is transferred with the most significant bit (msb) first. if a receiver (external device or NT68P61A) cannot receive another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line scl low to force the transmitter into a wait state. data transfer then continues when the receiver is ready for another byte of data and release clock line scl. each byte data is followed by an acknowledge bit. acknowledge: the acknowledgment will be generated at ninth clock by whom receive data. in the write mode, NT68P61A system must respond to this acknowledgment. after receiving one byte data from external device, NT68P61A will automatically send an acknowledgment by pulling sda line to 'low'. in the read mode, external device must respond to this acknowledgment and at every byte data sent, user can read rxak bit in iists register to check if external sent a ack or not. the intd interrupt: after NT68P61A receive the start condition, it w ill generate an intd interrupt at the falling edge of the ninth clock. user can control the flow of ddc2b transmission at this intd interrupt. the intd on the write mode: NT68P61A read data from external device. at intd interrupt, the scl will be hold low by NT68P61A. when getting one byte data from ii_dat register, user can write '00' into ii_dat register and the scl w ill be released. external device can continue sending next byte data to NT68P61A. refer to figure 24. the intd on the read mode: external device read data from NT68P61A. at intd interrupt, the scl will be hold low by NT68P61A. user can check rxack bit in the iists register whether external device has sent an ack or not after one byte data transfer. if external device has sent an ack, the rxack will be '0' (assume the acknowledgment is low signal). when user puts one new byte data into ii_dat register, the scl will be released for generation of scl transmission clock. the next byte data will be shifted out properly. refer to figure 25.
NT68P61A 39 stop condition: when scl & sda lines have been released (remain in 'high' state), ddc2b data transfer is always terminated by a stop condition generated by external device. a stop signal is defined as a low to high transition of sda while scl is in high state. when there is a stop condition, NT68P61A w ill set the 'stop' bit to '1' and user can poll this status bit to control ddc2b transmission at any time. this bit keeps '1' until user clears it. notice the scl and sda lines must conform to i 2 c bus specifications. (refer to figure 26). refer to the standard i 2 c bus specification for details. changing to ddc1 mode: after an external device terminates ddc2 transmission, set mdi/ 2 to 1 for changing to dcc1 mode. when the scl line has been released (pulled-up), user can force NT68P61A to ddc1 mode communication at any time. this function is supporting the 'error' recovery protocol in the vesa ddc standard ver 2.0. control bit description: addr. register init bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 $0005 md con 07h - - - - - - - - - insen - hsel s/ c s/ c md1/ 2 md1/ 2 r w $000f iex 00h - - ieints ieintd ieinta ieintr ieinte ieintv w $0010 irqx 00h - - irqints irqintd irqinta irqintr irqinte irqintv r $0011 clr flg 00h clrhov clrvov clrints clrintd clrinta clrintr clrinte clrintv w $0013 ii adr ffh ar7 ar6 ar5 ar4 ar3 ar2 ar1 - w $0014 ii dat 00h sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rw $0015 ii sts 08h - - start start stop stop enddc trx rxak - r w mdcon control register: md1/ 2 : select the ddc mode - '1' for ddc1 and '0' for ddc2b mode. system w ill be ddc1 mode by default. when transmission mode is changed form ddc1 to ddc2b, system w ill automatically clear this bit. iex control register: in ddc2 mode, user use ints, inta & intd interrupt and ii_sts control register to control ddc2b transmission. ii_dat control register: data buffer for transmission ii_adr control register: user can define the address of ddc2b device. if an external device sends the same address data as this control register (calling NT68P61A), NT68P61A will generate an inta interrupt. ii_sts control register: enddc : when clearing this bit, the system w ill activate ddc transmission. p30 and p31 w ill switch to sda and scl pin. trx: in the read mode of ddc2b transmission, user must set this bit '1'. rxak: in the write mode of ddc2b transmission, after one byte has been sent out to the sda line, there will be an intd interrupt. at intd interrupt service routine, user can check this bit to see if external device has responded to NT68P61A.
NT68P61A 40 10100000 scl sda (external device) data data start stop ints inta intd sda (NT68P61A) aaa r/w wait wait wait wait (b) write_mode timing diagram (a) write_mode data format data 0 a a a data transferred from external device from external device to NT68P61A from NT68P61A to external device a = acknowledge s = start p = stop NT68P61A address sr/w data p figure 24. ddc2b write_mode spec .
NT68P61A 41 10100001 scl sda (external device) data data start stop ints inta intd sda (NT68P61A) a r/w wait wait wait wait (b) read_mode timing diagram (a) read_mode data format data p 1 a a data transferred from external device from external device to NT68P61A from NT68P61A to external device a = acknowledge a = no acknowledge ? ? ??a? ? ? ??e? a a s NT68P61A address r/w data a figure 25. ddc2b read_mode spec .
NT68P61A 42 open intv & ints wait interrupt or doing something main program interrupt service routine polling ints ? ddc2 yes no open inta & intr change to ddc2 mode md 1/2 = 0 (auto switch) put addr. into iiadr reg. intv ? open ints & intd ddc1 yes no reset edid buffer index put one byte data into iidat reg. change to ddc1 mode md_con = 1 no return yes ddc2 operate over ? yes open inta & intv ddc1 transfer ? yes yes no no ddc2b write_mode operation ? from edid buffer index put one byte data into iidat reg. read one byte data from iidat reg. to set edid buffer index write '00' to iidat for releasing scl inta ? yes open inta & intd reset edid buffer index from iidat reg. lsb to decide write/read mode yes no put first byte data into iidat reg. for releaseing scl & for transfer data no other int. service no from edid buffer index put one byte data into iidat reg. yes yes yes yes no no no no need polling ints ? need polling inta ? open inta & intd need polling intd ? intd ? write '00' to iidat for releasing scl setting iists: trx = 0 (recv. mode) setting iists: trx = 0 (recv. mode) ddc2b read_mode operation ddc2b write_mode operation ? setting iists: trx = 1 (trans. mode) need polling intv ? set enddc = 0 open ints & intd reset edid buffer index need polling intr ? intr ? ddc2 idle for 2 sec. ? return to ddc1 mode open intv no no yes yes yes no figure 26. ddc1/2b software flow chart
NT68P61A 43 absolute maximum ratings* dc supply voltage v dd - v ss . . . . . . . . . . . .-0.3v to 7v input voltage . . . . . . . . . . . . . . gnd -0.2v to v cc +0.2v operating temperature . . . . . . . . . . . . . . . . 0 c to +70 c storage temperature . . . . . . . . . . . . . . . -50 c to +125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposed to the absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics (v dd = 5v, t a = 25 c, oscillator freq. = 8mhz, unless otherwise specified) symbol parameter min . typ. max . unit conditions i dd operating current 20 ma no loading vih1 input high voltage 2 v p00 - p07, p10-p16, p20-p27, p30, p31, reset , vsynci, hsynci, halfhi, inte vih2 input high voltage 3 v scl, sda pins vil1 input low voltage 0.8 v p00 - p07, p10 - p16, p20 - p27, p30, p31, reset , vsynci, hsynci, halfhi, inte vil2 input low voltage 1.5 v scl, sda pins iih input high current -200 -350 m a p00 - p07, p10 - p16 ,p20 -p27, vsynci, hsynci, halfhi, reset (vih = 2.4v) voh1 output high voltage 2.4 v p00 - p07, p10 - p15 (i oh = -100 m a) vsynco, hsynco (i oh = -4ma) halfho (i oh = -4ma) p20-p27 (i oh = -10ma) voh2 output high voltage (dac8 - dac13) 5 v external applied voltage voh3 output high voltage (dac0 - dac7) 12 v external applied voltage vol output low voltage 0.4 v p00 - p07, p10 - p15, dac0 - 13 (i ol = 4ma) scl/p30, sda/p31 (i ol = 5ma) vsynco, hsynco (i ol = 4ma) halfho (i ol = 4ma) p20 - p27 (i ol = 10ma) vlvr low voltage threshold 4.0 v rol pull down resistor ( reset ) 25k 50k 75k w roh1 pull up resistor (inte) 11k 22k 33k w roh2 pull up resistor (port0 & port1) 11k 22k 33k w roh3 pull up resistor (hsynci & vsynci) 11k 22k 33k w
NT68P61A 44 ac electrical characteristics (v dd = 5v, t a = 25 c, oscillator freq. = 8mhz, unless otherwise specified) symbol parameter min. typ. max. unit condition fsys system clock 8 mhz t cnvt a/d conversion time 375 m s voffset a/d converter offset error 39 mv vin = 2v for a/d converter vlinear a/d input dynamic range of linearity conversion 0.3 0.7 v dd tinst the inserted hsync pulse width 2 m s composite sync (refer figure 18) tdev the time deviation at the end edge of inserted hsync pulse 250 ns composite mode & insertion function activated t reset reset pulse width low 2 t cycle t cycle = 2/fsys fvsync vsync input frequency 32 25k hz t vsync = 1/fvsync t vpw vsync input pulse width 8 300 m s fhsync hsync input frequency 30 120 khz t hsync = 1/fhsync t hpw1 hsync input pulse width high 0.5 7 m s t hpw2 hsync input pulse width low 8 m s composite sync t error1 counting deviation of base timer 1 m s1 m s clock source t error2 counting deviation of base timer 1 ms 1ms clock source
NT68P61A 45 ddc1 mode symbol parameter min. typ. max. unit condition t vpw vsync high time 0.5 300 us fvsync vsync input frequency 32 25k hz t vsync = 1/fvsync t dd data valid 200 500 ns t mode time for transition to ddc2b mode 500 ns bit 0 null bit bit 7 bit 6 scl sda vsync t mode t dd t vpw composite hsync input extracted vsync output (no loading) ? ? ? t hpw1 t hpw2
NT68P61A 46 ddc2b mode symbol parameter min. typ. max. unit fscl scl clock frequency 100 khz t buf bus free between a stop and start condition 4.7 m s t hd ; sta hold time for start condition 4 m s t low low period of the scl clock 4.7 m s t high high period of the scl clock 4 m s t su ; sta set-up time for a repeated start condition 4.7 m s t hd ; dat data hold time 300 ns t su ; dat data set-up time 300 ns t r rise time of both sda and scl signals 1 m s t f fall time of both sda and scl signals 300 ns t su ; sto set-up time for stop condition 4 m s scl sda t buf t hd ; sta t su ; dat t high t r t f t hd ; dat t low stop start t su ; sta t hd ; sta stop t su ; sto start
NT68P61A 47 ordering information part no. package NT68P61A 40l dip
NT68P61A 48 package information dip 40l outline dimensions unit: inches/mm 1 21 40 e 1 s a 2 a l e e a d c a b 1 b a 1 base plane seating plane 20 e 1 symbol dimensions in inches dimensions in mm a 0.210 max. 5.33 max. a 1 0.010 min. 0.25 min. a 2 0.1550.010 3.940.25 b 0.018 +0.004 0.46 +0.10 -0.002 -0.05 b 1 0.050 +0.004 1.27 +0.10 -0.002 -0.05 c 0.010 +0.004 0.25 +0.10 -0.002 -0.05 d 2.055 typ. (2.075 max.) 52.20 typ. (52.71 max.) e 0.6000.010 15.240.25 e 1 0.550 typ. (0.562 max.) 13.97 typ. (14.27 max.) e 1 0.1000.010 2.540.25 l 0.1300.010 3.300.25 a 0 ~ 15 0 ~ 15 e a 0.6550.035 16.640.89 s 0.093 max. 2.36 max. notes: 1. the maximum value of dimension d includes end flash. 2. dimension e 1 does not include resin fins. 3. dimension s includes end flash.

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